This improved system bus structure relates generally to computers, and more particularly, to system bus structures for parallel signal transfers between devices as in multi-application mini-supercomputer systems of the type including at least one general purpose system bus structure for carrying as many as 128 simultaneous signals to and from various units connected to the system bus.
In the past those skilled in the art have achieved high performance parallel computational power, by using one or more architectural classes of supercomputers: pipelined computers, array processors, vector processors and multiprocessor systems. A pipelined computer performs overlapped computations to exploit temporal parallelism, while an array processor uses multiple arithmetic/logic units to achieve spatial parallelism. A vector processor uses large vector registers to facilitate repetitive arithmetic operations on groups or vectors of numeric operands. A multiprocessor system has multiple instruction streams over a set of interactive processors with shared resources (memories, databases, etc.). Each of the systems is designed to offer improved performance for particular applications over a non-pipelined single processor digital computer, but not in other applications. Furthermore, the expense of supercomputers is very high in terms of initial cost, maintenance, and space.
There is a need for a lower cost computer having supercomputer capabilities and there is a further need for such a computer with a substantial capability to be utilized in many diverse applications.
One of the most crucial impediments to improved performance of the super minicomputer has been the system bus structure design and methods for transferring signals over the system bus structure. During the past few years, there have been a number of attempts to solve the problems associated with the methods of communicating in multi-unit and multi-processor environments, but, generally speaking, they have only solved limited problems in limited applications.
For instance, U.S. Pat. No. 4,233,366 to Levy teaches a synchronous system bus structure that requires each of the system bus units connected to the system bus to sample each of the request signals and to conduct its own arbitration, rather than to have a centralized arbitration and control unit, and further does not discuss any enablement for a system network.
The instant assignee and its predecessor in interest have produced and sold a digital computer having a system bus structure with a two-board design, referred to as the Concept series, which transferred data as 32-bit words but lacked the capability of transferring 64 or 128-bit words at one time. The prior Concept computers also employed independent unit arbitration rather than centralized arbitration.
Accordingly, there is a need for a system bus structure for use in a variety of inexpensive mini-supercomputer architectures including diverse applications and that is designed to support high speed, high reliability, parallel processing of bi-directional 64 and 128-bit signal transfers in a multi-port and multiple central processor unit (CPU) environment.